1031 search results - page 165 / 207 » Broadcasting with Selective Reduction |
ISVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
FPL
2007
Springer
14 years 4 months ago
2007
Springer
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
VTS
2006
IEEE
14 years 4 months ago
2006
IEEE
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
ACIVS
2006
Springer
14 years 4 months ago
2006
Springer
The nearest neighbor (NN) classifier is well suited for generic object recognition. However, it requires storing the complete training data, and classification time is linear in ...