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» Buffered Crossbar Fabrics Based on Networks on Chip
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MICRO
2008
IEEE
131views Hardware» more  MICRO 2008»
14 years 2 months ago
Token flow control
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha
ISCC
2007
IEEE
127views Communications» more  ISCC 2007»
14 years 1 months ago
Head-to-Tail: Managing Network Load through Random Delay Increase
Window-based congestion control is typically based on exhausting bandwidth capacity, which occasionally leads to transient congestion. Moreover, flow synchronization may deteriora...
Stylianos Dimitriou, Vassilis Tsaoussidis
CASES
2004
ACM
14 years 1 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
FPL
2005
Springer
226views Hardware» more  FPL 2005»
14 years 1 months ago
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...
CLUSTER
2000
IEEE
14 years 1 days ago
Design and Performance of Maestro Cluster Network
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada