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QEST
2007
IEEE
14 years 1 months ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
DAC
2007
ACM
14 years 8 months ago
Layered Switching for Networks on Chip
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
Zhonghai Lu, Ming Liu, Axel Jantsch
NOCS
2007
IEEE
14 years 1 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
NOCS
2008
IEEE
14 years 2 months ago
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang,...
ISQED
2007
IEEE
109views Hardware» more  ISQED 2007»
14 years 1 months ago
Virtual Channels Planning for Networks-on-Chip
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
Ting-Chun Huang, Ümit Y. Ogras, Radu Marcules...