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» Building the functional performance model of a processor
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EMSOFT
2004
Springer
14 years 2 months ago
Model based estimation and verification of mobile device performance
Performance is an important quality attribute that needs to be and managed proactively. Abstract models of the system are not very useful if they do not produce reasonably accurat...
Gopalakrishna Raghavan, Ari Salomaki, Raimondas Le...
DAC
1992
ACM
14 years 21 days ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
DAC
2006
ACM
13 years 10 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 1 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
SMA
2009
ACM
163views Solid Modeling» more  SMA 2009»
14 years 3 months ago
Multi-core collision detection between deformable models
We present a new parallel algorithm for interactive and continuous collision detection between deformable models. Our algorithm performs incremental hierarchical computations betw...
Min Tang, Dinesh Manocha, Ruofeng Tong