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» Building the functional performance model of a processor
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ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
14 years 2 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
GECCO
2010
Springer
180views Optimization» more  GECCO 2010»
14 years 2 days ago
Comparison of NEWUOA with different numbers of interpolation points on the BBOB noisy testbed
In this paper, we study the performances of the NEW Unconstrained Optimization Algorithm (NEWUOA) with different numbers of interpolation points. NEWUOA is a trust region method, ...
Raymond Ros
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 1 months ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
CAV
2009
Springer
215views Hardware» more  CAV 2009»
14 years 9 months ago
Homer: A Higher-Order Observational Equivalence Model checkER
We present HOMER, an observational-equivalence model checker for the 3rd-order fragment of Idealized Algol (IA) augmented with iteration. It works by first translating terms of the...
David Hopkins, C.-H. Luke Ong
ICDE
2006
IEEE
215views Database» more  ICDE 2006»
14 years 10 months ago
cgmOLAP: Efficient Parallel Generation and Querying of Terabyte Size ROLAP Data Cubes
In this demo we present the cgmOLAP server, the first fully functional parallel OLAP system able to build data cubes at a rate of more than 1 Terabyte per hour. cgmOLAP incorporat...
Ying Chen, Andrew Rau-Chaplin, Frank K. H. A. Dehn...