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» Bus Architectures for Safety-Critical Embedded Systems
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DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 12 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
DATE
2010
IEEE
149views Hardware» more  DATE 2010»
14 years 17 days ago
Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems
—As Electronic Control Units (ECUs) and embedded software functions within an automobile keep increasing in number, the scale and complexity of automotive embedded systems is gro...
Karthik Lakshmanan, Gaurav Bhatia, Ragunathan Rajk...
DAC
2000
ACM
14 years 8 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
MAM
2002
110views more  MAM 2002»
13 years 7 months ago
Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm
The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeline...
Ernesto Martins, Paulo A. C. S. Neves, José...
FDL
2007
IEEE
14 years 1 months ago
Mapping Actor-Oriented Models to TLM Architectures
Actor-oriented modeling approaches are convenient for implementing functional models of embedded systems. Architectural models for heterogeneous system-on-chip architectures, howe...
Jens Gladigau, Christian Haubelt, Bernhard Niemann...