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DAC
2006
ACM
14 years 1 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 1 months ago
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design
UML is gaining increased attention as a system design language, as indicated by current standardization activities such as the SysML initiative and the UML for SoC Forum. Moreover...
Yves Vanderperren, Wim Dehaene
FDL
2005
IEEE
14 years 1 months ago
Integrating Model-Checking with UML-based SoC Development
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...
Peter Green, Kinika Tasie-Amadi
ICIAR
2005
Springer
14 years 1 months ago
Vector Median Root Signals Determination for cDNA Microarray Image Segmentation
Abstract. This paper presents a new cDNA microarray image segmentation framework. The framework uses robust vector median filtering to generate a root sigLnal which is an image ob...
Rastislav Lukac, Konstantinos N. Plataniotis
SAMOS
2004
Springer
14 years 28 days ago
A High-Level Programming Paradigm for SystemC
The SystemC language plays an increasingly important role in the system-level design domain, facilitating designers to start with modeling and simulating system components and thei...
Mark Thompson, Andy D. Pimentel