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114
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ISCA
2010
IEEE
237views Hardware» more  ISCA 2010»
15 years 1 months ago
High performance cache replacement using re-reference interval prediction (RRIP)
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely J...
ISCA
2010
IEEE
216views Hardware» more  ISCA 2010»
15 years 1 months ago
The impact of management operations on the virtualized datacenter
Virtualization has the potential to dramatically reduce the total cost of ownership of datacenters and increase the flexibility of deployments for general-purpose workloads. If pr...
Vijayaraghavan Soundararajan, Jennifer M. Anderson
139
Voted
ISPDC
2010
IEEE
15 years 1 months ago
Resource-Aware Compiler Prefetching for Many-Cores
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
George C. Caragea, Alexandros Tzannes, Fuat Keceli...
115
Voted
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
15 years 1 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...
146
Voted
JAIR
2010
160views more  JAIR 2010»
15 years 1 months ago
Reasoning About the Transfer of Control
We present DCL-PC: a logic for reasoning about how the abilities of agents and coalitions of agents are altered by transferring control from one agent to another. The logical foun...
Wiebe van der Hoek, Dirk Walther, Michael Wooldrid...
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