99 search results - page 6 / 20 » CAD Directions for High Performance Asynchronous Circuits |
121
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ASYNC
2002
IEEE
15 years 8 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
112
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DAC
1996
ACM
15 years 7 months ago
1996
ACM
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
117
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ASYNC
2003
IEEE
15 years 8 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
123
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GLVLSI
2009
IEEE
15 years 7 months ago
2009
IEEE
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
113
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FPGA
2009
ACM
15 years 10 months ago
2009
ACM
Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architect...