44 search results - page 5 / 9 » CAD challenges for 3D ICs |
142
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ISVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
132
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GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
138
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GLVLSI
2009
IEEE
2009
IEEE
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
16 years 11 days ago
This paper discusses the impact of migrating from 2-D to 3-D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3-...
155
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DAC
2007
ACM
15 years 9 months ago
2007
ACM
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a repl...
313
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DAC
2011
ACM
14 years 5 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...