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ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
14 years 23 days ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi
DAC
2003
ACM
14 years 1 months ago
Fast timing-driven partitioning-based placement for island style FPGAs
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
DAC
2004
ACM
14 years 9 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 1 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati