416 search results - page 17 / 84 » CMOL FPGA circuits |
GLVLSI
2005
IEEE
14 years 4 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
FPL
2011
Springer
12 years 10 months ago
2011
Springer
Abstract—Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and offer, at the same time, a mo...
ARC
2012
Springer
12 years 6 months ago
2012
Springer
Computing cores to be implemented on FPGAs may involve divisions by small integer constants in fixed or floating point. This article presents a family of architectures addressing...
JUCS
2007
13 years 10 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
SLIP
2009
ACM
14 years 5 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...