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FPL
1997
Springer
125views Hardware» more  FPL 1997»
14 years 3 months ago
VPR: A new packing, placement and routing tool for FPGA research
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
Vaughn Betz, Jonathan Rose
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
14 years 5 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
FPGA
2006
ACM
113views FPGA» more  FPGA 2006»
14 years 2 months ago
Optimality study of logic synthesis for LUT-based FPGAs
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
Jason Cong, Kirill Minkovich
FPL
2005
Springer
79views Hardware» more  FPL 2005»
14 years 4 months ago
FPGA-based implementation and comparison of recursive and iterative algorithms
The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely ...
Valery Sklyarov, Iouliia Skliarova, Bruno Figueire...
AHS
2006
IEEE
133views Hardware» more  AHS 2006»
14 years 5 months ago
Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...
Justin Lee, Joaquin Sitte