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GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
14 years 3 months ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...
APCCAS
2002
IEEE
92views Hardware» more  APCCAS 2002»
14 years 2 months ago
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA
This paper proposes a new region extraction algorithm based on cellular automaton operation, which only utilizes the region boundary information of the image. A simple pixel circu...
Teppei Nakano, Takashi Morie, Makoto Nagata, Atsus...
FPL
2009
Springer
152views Hardware» more  FPL 2009»
14 years 2 months ago
Clock gating architectures for FPGA power reduction
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
Safeen Huda, Muntasir Mallick, Jason H. Anderson
DFT
1999
IEEE
125views VLSI» more  DFT 1999»
14 years 2 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...
FPL
2006
Springer
115views Hardware» more  FPL 2006»
14 years 1 months ago
A Congestion Driven Placement Algorithm for FPGA Synthesis
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
Yue Zhuo, Hao Li, Saraju P. Mohanty