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ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 3 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 3 months ago
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
John W. Lockwood, Christopher E. Neely, Christophe...
AINA
2010
IEEE
14 years 2 months ago
The Cost Effective Pre-processing Based NFA Pattern Matching Architecture for NIDS
—Network Intrusion Detection System (NIDS) is a system which can detect network attacks resulted from worms and viruses on the Internet. An efficient pattern matching algorithm p...
Yeim-Kuan Chang, Chen-Rong Chang, Cheng-Chien Su
FPL
2009
Springer
96views Hardware» more  FPL 2009»
14 years 2 months ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...
FPL
2001
Springer
96views Hardware» more  FPL 2001»
14 years 2 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...