869 search results - page 115 / 174 » Cache Architectures for Reconfigurable Hardware |
IPPS
2002
IEEE
14 years 17 days ago
2002
IEEE
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
CVPR
1998
IEEE
14 years 9 months ago
1998
IEEE
We have designed and implemented a system for real-time detection of 2-D features on a reconfigurable computer based on Field Programmable Gate Arrays (FPGA `s). We envision this ...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
DFT
2008
IEEE
14 years 2 months ago
2008
IEEE
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...
IPPS
2003
IEEE
14 years 28 days ago
2003
IEEE
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...