869 search results - page 157 / 174 » Cache Architectures for Reconfigurable Hardware |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
MICRO
1999
IEEE
13 years 11 months ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
ICT
2004
Springer
14 years 26 days ago
2004
Springer
The Resilient Packet Ring IEEE 802.17 is an evolving standard for the construction of Local and Metropolitan Area Networks. The RPR protocol scales to the demands of future packet ...