Sciweavers

869 search results - page 82 / 174
» Cache Architectures for Reconfigurable Hardware
Sort
View
92
Voted
DSN
2008
IEEE
15 years 9 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
104
Voted
DAC
2001
ACM
16 years 3 months ago
Re-Configurable Computing in Wireless
Wireless communications requires a new approach to implement the algorithms for new standards. The computational demands of these standards are outstripping the ability of traditi...
Bill Salefski, Levent Caglar
120
Voted
DSD
2010
IEEE
141views Hardware» more  DSD 2010»
15 years 22 days ago
Adaptive Beamforming Using the Reconfigurable MONTIUM TP
Until a decade ago, the concept of phased array beamforming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perfor...
Marcel D. van de Burgwal, Kenneth C. Rovers, Koen ...
171
Voted
ICES
2010
Springer
277views Hardware» more  ICES 2010»
15 years 21 days ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
130
Voted
SAMOS
2007
Springer
15 years 8 months ago
Online Prediction of Applications Cache Utility
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
Miquel Moretó, Francisco J. Cazorla, Alex R...