869 search results - page 85 / 174 » Cache Architectures for Reconfigurable Hardware |
FPL
2009
Springer
14 years 1 months ago
2009
Springer
The reconfigurable mesh model for massively parallel computing has recently been rediscovered and proposed as the basis of a practical many-core architecture. With this paper, we...
VTS
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
FPL
2007
Springer
14 years 3 months ago
2007
Springer
This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium R processor. This shows that the IDCT i...
ICMCS
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area...