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» Cache Architectures for Reconfigurable Hardware
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DSD
2010
IEEE
190views Hardware» more  DSD 2010»
13 years 9 months ago
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
I. Sajid, Sotirios G. Ziavras, M. M. Ahmed
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 2 months ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
14 years 1 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
ASAP
2008
IEEE
117views Hardware» more  ASAP 2008»
13 years 11 months ago
Reconfigurable acceleration of microphone array algorithms for speech enhancement
Microphone arrays play an important role in noise reduction and speech enhancement. Their algorithms are based on beamforming, which reduces the level of localized and ambient noi...
Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao...
DAIS
2010
13 years 10 months ago
A Reconfiguration Language for Virtualized Grid Infrastructures
The growing needs in computational power to answer to the increasing number of on-line services and the complexity of applications makes it mandatory to build corresponding hardwar...
Rémy Pottier, Marc Léger, Jean-Marc ...