67 search results - page 7 / 14 » Cache Performance of Combinator Graph Reduction |
SIGGRAPH
1994
ACM
13 years 11 months ago
1994
ACM
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper we introduce a new algorithm for model order reduction in the presence of parameter or process variation. Our analysis is performed using a graph interpretation of t...
ASAP
2006
IEEE
13 years 9 months ago
2006
IEEE
In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia appl...
USENIX
2007
13 years 10 months ago
2007
This paper focuses on evaluation of the effectiveness of optimization at various layers of the IO path, such as the file system, the device driver scheduler, and the disk drive i...