83 search results - page 8 / 17 » Cache Replacement with Dynamic Exclusion |
SIGARCH
2008
13 years 7 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
USENIX
1994
13 years 9 months ago
1994
We considerhowtoimprovetheperformanceof le cachingbyallowinguser-levelcontrolover lecache replacementdecisions. Weusetwo-levelcachemanagement: the kernel allocates physical pages ...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...