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» Cache modeling in probabilistic execution time analysis
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DATE
2010
IEEE
107views Hardware» more  DATE 2010»
14 years 22 days ago
Worst case delay analysis for memory interference in multicore systems
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...
Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia...
PSTV
1992
113views Hardware» more  PSTV 1992»
13 years 8 months ago
Coverage Preserving Reduction Strategies for Reachability Analysis
We study the effect of three new reduction strategies for conventional reachability analysis, as used in automated protocol validation algorithms. The first two strategies are imp...
Gerard J. Holzmann, Patrice Godefroid, Didier Piro...
CGO
2004
IEEE
13 years 11 months ago
Probabilistic Predicate-Aware Modulo Scheduling
Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transforma...
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Da...
HPCA
2006
IEEE
14 years 8 months ago
Completely verifying memory consistency of test program executions
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
Chaiyasit Manovit, Sudheendra Hangal
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
13 years 11 months ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...