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ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
14 years 4 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
DAC
2011
ACM
12 years 10 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
ICSE
2009
IEEE-ACM
14 years 4 months ago
Verifying networked programs using a model checker extension
Model checking finds failures in software by exploring every possible execution schedule. Until recently it has been mainly applied to stand-alone applications. This paper presen...
Watcharin Leungwattanakit, Cyrille Artho, Masami H...
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
14 years 4 months ago
Synthesizing Synchronous Elastic Flow Networks
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
Greg Hoover, Forrest Brewer
WDAG
2005
Springer
82views Algorithms» more  WDAG 2005»
14 years 3 months ago
Distributed Transactional Memory for Metric-Space Networks
Transactional Memory is a concurrent programming API in which concurrent threads synchronize via transactions (instead of locks). Although this model has mostly been studied in the...
Maurice Herlihy, Ye Sun