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DATE
2004
IEEE
159views Hardware» more  DATE 2004»
13 years 11 months ago
Compositional Memory Systems for Data Intensive Applications
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
12 years 11 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
CAL
2007
13 years 7 months ago
A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed memory hierarchy enhancements for coher...
Jason Zebchuk, Andreas Moshovos
CGO
2003
IEEE
13 years 11 months ago
METRIC: Tracking Down Inefficiencies in the Memory Hierarchy via Binary Rewriting
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
Jaydeep Marathe, Frank Mueller, Tushar Mohan, Bron...
CF
2010
ACM
13 years 10 months ago
Global management of cache hierarchies
Cache memories currently treat all blocks as if they were equally important, but this assumption of equally importance is not always valid. For instance, not all blocks deserve to...
Mohamed Zahran, Sally A. McKee