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ASAP
2006
IEEE
134views Hardware» more  ASAP 2006»
13 years 9 months ago
Buffer and register allocation for memory space optimization
In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia appl...
Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha...
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
14 years 1 months ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
ANCS
2010
ACM
13 years 5 months ago
A new TCB cache to efficiently manage TCP sessions for web servers
TCP/IP, the most commonly used network protocol, consumes a significant portion of time in Internet servers. While a wide spectrum of studies has been done to reduce its processin...
Guangdeng Liao, Laxmi N. Bhuyan, Wei Wu, Heeyeol Y...
TVLSI
2010
13 years 2 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
DAC
1997
ACM
13 years 11 months ago
Remembrance of Things Past: Locality and Memory in BDDs
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...
Srilatha Manne, Dirk Grunwald, Fabio Somenzi