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DAC
2005
ACM
14 years 11 months ago
High performance encryption cores for 3G networks
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
René Cumplido, Tomás Balderas-Contre...
ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
14 years 3 months ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
EGH
2003
Springer
14 years 3 months ago
An effective hardware architecture for bump mapping using angular operation
In this paper, we propose an effective bump mapping algorithm that utilizes the reference space with the polar coordinate system and also propose a new hardware architecture assoc...
S. G. Lee, W. C. Park, W. J. Lee, T. D. Han, S. B....
DSD
2009
IEEE
141views Hardware» more  DSD 2009»
13 years 7 months ago
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
Ozgur Tasdizen, Ilker Hamzaoglu
IJCNN
2000
IEEE
14 years 2 months ago
Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Te...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...