This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
In this paper, we propose an effective bump mapping algorithm that utilizes the reference space with the polar coordinate system and also propose a new hardware architecture assoc...
S. G. Lee, W. C. Park, W. J. Lee, T. D. Han, S. B....
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Te...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...