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DAC
2006
ACM
14 years 11 months ago
Timing-driven Steiner trees are (practically) free
Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...
Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sz...
DAC
2006
ACM
14 years 11 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
DAC
2006
ACM
14 years 11 months ago
BoxRouter: a new global router based on box expansion and progressive ILP
In this paper, we propose a new global router, BoxRouter, powered by the concept of box expansion and progressive integer linear programming (ILP). BoxRouter first uses a simple P...
Minsik Cho, David Z. Pan
DAC
2006
ACM
14 years 11 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
DAC
2006
ACM
14 years 11 months ago
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N...