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ETS
2007
IEEE
14 years 1 months ago
2007
IEEE
— The growth in System-on-Chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an impor...
FPT
2005
IEEE
14 years 1 months ago
2005
IEEE
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The meth...
ISQED
2002
IEEE
14 years 16 days ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...