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IPPS
2002
IEEE
14 years 15 days ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
OOPSLA
2007
Springer
14 years 1 months ago
Modular typestate checking of aliased objects
Objects often define usage protocols that clients must follow in order for these objects to work properly. Aliasing makes it notoriously difficult to check whether clients and i...
Kevin Bierhoff, Jonathan Aldrich
ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
11 years 10 months ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...
IFL
2001
Springer
146views Formal Methods» more  IFL 2001»
14 years 14 hour ago
Optimizations on Array Skeletons in a Shared Memory Environment
Map- and fold-like skeletons are a suitable abstractions to guide parallel program execution in functional array processing. However, when it comes to achieving high performance, i...
Clemens Grelck
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
14 years 1 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra