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CF
2010
ACM
14 years 21 days ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
MAM
2002
63views more  MAM 2002»
13 years 7 months ago
OPTS: increasing branch prediction accuracy under context switch
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors. Though many dynamic branch predictors have been proposed to obtain high...
Moon-Sang Lee, Young-Jae Kang, Joonwon Lee, Seung ...
SIGMETRICS
2009
ACM
103views Hardware» more  SIGMETRICS 2009»
14 years 2 months ago
Restrained utilization of idleness for transparent scheduling of background tasks
A common practice in system design is to treat features intended to enhance performance and reliability as low priority tasks by scheduling them during idle periods, with the goal...
Ningfang Mi, Alma Riska, Xin Li, Evgenia Smirni, E...
CAL
2006
13 years 7 months ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
MICRO
2007
IEEE
108views Hardware» more  MICRO 2007»
14 years 1 months ago
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...