43 search results - page 3 / 9 » Capacitive Leadframe Testing |
DFT
2003
IEEE
14 years 11 days ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
In order to optimize interconnect to avoid signal integrity problems, very fast and accurate 3-D capacitance extraction is essential. Fast algorithms, such as the multipole or prec...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
EOR
2010
13 years 7 months ago
2010
In this work we study the Capacitated p-Center Problem (CpCP) and we propose an exact algorithm to solve it. We study two auxiliary problems and their relation to CpCP, and we pro...