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DAC
2007
ACM
14 years 10 months ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu
DAC
2007
ACM
14 years 10 months ago
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...
DAC
2007
ACM
14 years 10 months ago
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs
In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient,...
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu...
DAC
2003
ACM
14 years 10 months ago
Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kun...
DAC
2003
ACM
14 years 10 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...