A survey of techniques for energy efficient on-chip communication

Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanisms, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC d...

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Vijay Raghunathan, Mani B. Srivastava, Rajesh K. Gupta
• Keywords: DAC 2003, Design Automation, Efficient On-chip Communication, On-chip Interconnects, SoC Communication Architectures