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ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 3 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
CF
2010
ACM
14 years 2 months ago
Towards greener data centers with storage class memory: minimizing idle power waste through coarse-grain management in fine-grai
Studies have shown much of today’s data centers are over-provisioned and underutilized. Over-provisioning cannot be avoided as these centers must anticipate peak load with burst...
In Hwan Doh, Young Jin Kim, Jung Soo Park, Eunsam ...
CODES
2009
IEEE
14 years 1 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...