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» Cell architecture for nanoelectronic design
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CF
2006
ACM
13 years 11 months ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
SAC
2009
ACM
14 years 2 months ago
Celling SHIM: compiling deterministic concurrency to a heterogeneous multicore
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
Nalini Vasudevan, Stephen A. Edwards
IPPS
2007
IEEE
14 years 1 months ago
Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems
Code compression has been applied to embedded systems to minimize the silicon area utilized for program memories, and lower the power consumption. More recently, it has become a n...
Nazish Aslam, Mark Milward, Ioannis Nousias, Tughr...
DAC
2004
ACM
14 years 8 months ago
Accurate pre-layout estimation of standard cell characteristics
With the advent of deep-submicron technologies, it has become essential to model the impact of physical/layout effects up front in all design flows [1]. The effect of layout paras...
Hiroaki Yoshida, Kaushik De, Vamsi Boppana
DAC
2006
ACM
14 years 8 months ago
A family of cells to reduce the soft-error-rate in ternary-CAM
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...
Navid Azizi, Farid N. Najm