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» Cell architecture for nanoelectronic design
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ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 9 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
ICES
1998
Springer
100views Hardware» more  ICES 1998»
13 years 11 months ago
Embryonics: A Macroscopic View of the Cellular Architecture
The ontogenetic development of living beings suggests the design of a new kind of multicellular automaton endowed with novel quasi-biological properties: self-repair and self-repli...
Daniel Mange, André Stauffer, Gianluca Temp...
ANSS
2001
IEEE
13 years 11 months ago
New Queuing Strategy for Large Scale ATM Switches
In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to ...
Mohsen Guizani, Ala I. Al-Fuqaha
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 1 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
DAC
2000
ACM
14 years 8 months ago
The role of custom design in ASIC Chips
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
William J. Dally, Andrew Chang