285 search results - page 4 / 57 » Cell architecture for nanoelectronic design |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the ...
CDES
2010
13 years 5 months ago
2010
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
PROCEDIA
2010
13 years 2 months ago
2010
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...