285 search results - page 50 / 57 » Cell architecture for nanoelectronic design |
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
The constant race for faster and more powerful CPUs is drawing to a close. No longer is it feasible to significantly increase the speed of the CPU without paying a crushing penalt...
VTC
2007
IEEE
14 years 1 months ago
2007
IEEE
— Hydra is a flexible wireless network testbed being developed at UT Austin. Our focus is networks that support multiple wireless hops and where the network, especially the MAC,...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...