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ISCA
2006
IEEE
148views Hardware» more  ISCA 2006»
14 years 4 months ago
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range ...
Christopher B. Colohan, Anastassia Ailamaki, J. Gr...
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
14 years 4 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
IV
2006
IEEE
104views Visualization» more  IV 2006»
14 years 4 months ago
Easy Grocery: 3D Visualization in e-Grocery
There are many deficiencies in the traditional electronic commerce schema. The main problem for consideration is the text and picture based design that underpins current HTML syst...
J. Somerville, Liz J. Stuart, N. Barlow
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 4 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
RTAS
2006
IEEE
14 years 4 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
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