Sciweavers

658 search results - page 13 / 132
» Challenges in Physical Chip Design
Sort
View
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 3 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
14 years 19 days ago
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
- For sub-90nm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/So...
Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvi...
ICCD
2005
IEEE
129views Hardware» more  ICCD 2005»
14 years 5 months ago
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC p...
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vi...
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
14 years 5 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
EDBT
2010
ACM
184views Database» more  EDBT 2010»
13 years 10 months ago
PARINDA: an interactive physical designer for PostgreSQL
One of the most challenging tasks for the database administrator is to physically design the database to attain optimal performance for a given workload. Physical design is hard b...
Cristina Maier, Debabrata Dash, Ioannis Alagiannis...