658 search results - page 20 / 132 » Challenges in Physical Chip Design |
112
Voted
IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
Expresso is an experiment management system that is designed to assist biologists in planning, executing, and interpreting microarray experiments. It serves as a unifying framewor...
122
Voted
ISCA
2007
IEEE
15 years 10 months ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
131
click to vote
DAC
2007
ACM
16 years 4 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
128
Voted
CAV
2009
Springer
15 years 10 months ago
2009
Springer
Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip desi...
169
Voted
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...