658 search results - page 24 / 132 » Challenges in Physical Chip Design |
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental ch...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
Creating functional tests that work on an ATE has always been a significant challenge [1]. This paper identifies the fundamental mechanisms for functional test failures of an SOC ...
ISVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
System-level design techniques promise a way to lessen the productivity gap between fabrication and design. Unfortunately, these techniques have been slow to catch on, in part bec...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Spatial image processing chips, known as silicon retinas, are based on the architecture of vertebrate retina and can be mathematically represented as the Laplacian of Gaussian (LO...