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» Challenges in Physical Chip Design
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DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 2 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
ASPDAC
2005
ACM
119views Hardware» more  ASPDAC 2005»
13 years 10 months ago
CMP aware shuttle mask floorplanning
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
ICRA
2008
IEEE
145views Robotics» more  ICRA 2008»
14 years 3 months ago
Towards a personal robotics development platform: Rationale and design of an intrinsically safe personal robot
—The most critical challenge for Personal Robotics is to manage the issue of human safety and yet provide the physical capability to perform useful work. This paper describes a n...
Keenan A. Wyrobek, Eric H. Berger, H. F. Machiel V...
SEDE
2007
13 years 10 months ago
BeLearning: Designing accessible web applications
Flexibility and adaptivity are two of the outstanding characteristics of new media and new technologies. These properties allow new methods to provide physically challenged people...
Helmut Vieritz, Sabina Jeschke
MICRO
2008
IEEE
114views Hardware» more  MICRO 2008»
14 years 3 months ago
Toward a multicore architecture for real-time ray-tracing
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting intera...
Venkatraman Govindaraju, Peter Djeu, Karthikeyan S...