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» Challenges in Physical Chip Design
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ISPASS
2007
IEEE
14 years 3 months ago
Modeling and Characterizing Power Variability in Multicore Architectures
Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors s...
Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ism...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 3 months ago
Life begins at 65: unless you are mixed signal?
The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, espe...
Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wass...
DAC
2005
ACM
13 years 10 months ago
Timing-driven placement by grid-warping
Grid-warping is a recent placement strategy based on a novel physical analogy: rather than move the gates to optimize their location, it elastically deforms a model of the 2-D chi...
Zhong Xiu, Rob A. Rutenbar
DATE
2003
IEEE
135views Hardware» more  DATE 2003»
14 years 2 months ago
Creating Value Through Test
Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing before the ICs are shipped to the cu...
Erik Jan Marinissen, Bart Vermeulen, Robert Madge,...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 1 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...