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» Challenges in Physical Chip Design
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CHES
2005
Springer
80views Cryptology» more  CHES 2005»
15 years 9 months ago
Successfully Attacking Masked AES Hardware Implementations
During the last years, several masking schemes for AES have been proposed to secure hardware implementations against DPA attacks. In order to investigate the effectiveness of thes...
Stefan Mangard, Norbert Pramstaller, Elisabeth Osw...
132
Voted
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
15 years 8 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
125
Voted
DAC
2000
ACM
16 years 4 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
129
Voted
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 10 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
128
Voted
SAC
2010
ACM
15 years 4 months ago
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
Pavel Ghosh, Arunabha Sen