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» Challenges in Physical Chip Design
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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 2 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
WS
2008
ACM
13 years 8 months ago
Recommendations based on semantically enriched museum collections
This article presents the CHIP demonstrator5 for providing personalized access to digital museum collections. It consists of three main components: Art Recommender, Tour Wizard, an...
Yiwen Wang, Natalia Stash, Lora Aroyo, Peter Gorge...
FPGA
2007
ACM
119views FPGA» more  FPGA 2007»
14 years 2 months ago
Synthesis of an application-specific soft multiprocessor system
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
Jason Cong, Guoling Han, Wei Jiang
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 2 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
SOSE
2006
IEEE
14 years 2 months ago
Service Oriented Evolutions and Analyses of Design Patterns
The globalization of software development helps to reduce business cost by outsourcing software design and development tasks. However, it also poses new challenges on the collabor...
Jing Dong, Sheng Yang, Dushyant S. Lad, Yongtao Su...