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» Challenges in Physical Chip Design
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DATE
2009
IEEE
183views Hardware» more  DATE 2009»
14 years 3 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
TCAD
2010
160views more  TCAD 2010»
13 years 3 months ago
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
DAC
2000
ACM
14 years 9 months ago
The role of custom design in ASIC Chips
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
William J. Dally, Andrew Chang
DAC
2000
ACM
14 years 9 months ago
System chip test: how will it impact your design?
A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challeng...
Yervant Zorian, Erik Jan Marinissen
DATE
2005
IEEE
152views Hardware» more  DATE 2005»
14 years 2 months ago
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges tha...
Fei Su, Krishnendu Chakrabarty