Sciweavers

197 search results - page 18 / 40
» Characterizing processor architectures for programmable netw...
Sort
View
FPL
2003
Springer
136views Hardware» more  FPL 2003»
14 years 24 days ago
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
Roland Höller
IMC
2010
ACM
13 years 5 months ago
Primitives for active internet topology mapping: toward high-frequency characterization
Current large-scale topology mapping systems require multiple days to characterize the Internet due to the large amount of probing traffic they incur. The accuracy of maps from ex...
Robert Beverly, Arthur Berger, Geoffrey G. Xie
DSD
2008
IEEE
139views Hardware» more  DSD 2008»
13 years 9 months ago
Revisiting the Cache Effect on Multicore Multithreaded Network Processors
Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new ...
Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. ...
CLUSTER
2008
IEEE
14 years 2 months ago
Context-aware address translation for high performance SMP cluster system
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
Moon-Sang Lee, Joonwon Lee, Seungryoul Maeng
MICRO
2008
IEEE
113views Hardware» more  MICRO 2008»
14 years 2 months ago
From SODA to scotch: The evolution of a wireless baseband processor
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, ...