Sciweavers

535 search results - page 62 / 107
» Checking Computations in Polylogarithmic Time
Sort
View
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
14 years 3 months ago
On the relation between simulation-based and SAT-based diagnosis
The problem of diagnosis – or locating the source of an error or fault – occurs in several areas of Computer Aided Design, such as dynamic verification, property checking, eq...
Görschwin Fey, Sean Safarpour, Andreas G. Ven...
GI
2004
Springer
14 years 2 months ago
Type Safe Programming of XML-based Applications
: There is an emerging amount of software for generating and manipulating XML documents. This paper addresses the problem of guaranteeing the validity of dynamically generated XML ...
Martin Kempa, Volker Linnemann
IEEEPACT
2002
IEEE
14 years 1 months ago
Eliminating Exception Constraints of Java Programs for IA-64
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komats...
ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
14 years 1 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
EUROCRYPT
1995
Springer
14 years 16 days ago
Quantum Oblivious Mutual Identification
We coiisider a situation where two parties, Alice and Bob, share a common secret string arid would like to mutually check their knowledge of that string. We describe a simple and e...
Claude Crépeau, Louis Salvail